In recent years, there is an increasing demand of improved device characteristics particularly in the field of analog integrated circuit devices. For example, there is a stringent demand in analog semiconductor integrated circuit devices for high precision of operational characteristics particularly in terms of threshold voltage and resistance values, in view of the fact that analog semiconductor integrated circuit devices have to guarantee high stability and controllability with regard to the threshold characteristics for the transistors formed therein and with regard to the resistance values for the resistance elements therein. Particularly, stable transistor characteristics and stable resistance values over long period of time are important in high precision analog semiconductor integrated circuit devices.
Meanwhile, a multilayer interconnection structure is used extensively these days in highly miniaturized semiconductor integrated circuit devices for electrical interconnection between semiconductor elements formed therein. In multilayer interconnection structure, interconnection patterns are formed in number of layers stacked with each other with intervening interlayer insulation films or SOG (spin-on-glass) films, wherein the interlayer insulation films are provided for electrical insulation between the interconnection patterns and for providing a planarized surface for formation of next interconnection patterns by burying the interconnection patterns of the current layer therein.
It is known that these interlayer insulation films contain a large amount of hydrogen and water in relation to the process of formation thereof. Thus, when such hydrogen or water is released from the interlayer insulation film with heat treatment conducted during the fabrication process of the semiconductor integrated circuit device and the released hydrogen or water molecules have reached the underlying polysilicon pattern forming a resistance element or gate electrode of a transistor, there is caused a substantial variation in the resistance value for the resistance element or threshold voltage for the transistor.
It is noted that when hydrogen molecules or water molecules thus released are trapped by the grain boundary of the polysilicon patterns, there would be caused significant modification in the characteristics of the resistance element or gate electrode of polysilicon due to the modified barrier height at the grain boundaries, while such modification of barrier height leads to increase or decrease of carrier concentration level in the polysilicon pattern. Because the influence caused by hydrogen or water depends on the concentration level of the impurity element introduced into the polysilicon pattern, the degree of the influence depends on the resistance value desired for the polysilicon pattern. Further, the amount of hydrogen incorporated into a polysilicon pattern depends on whether or not the polysilicon pattern is disposed right underneath a metal interconnection pattern functioning as a hydrogen barrier.
Patent Reference 1 discloses a voltage generation circuit that includes therein plural MOS (metal-oxide-semiconductor) transistors each having a polysilicon gate electrode. In Patent Reference 1, the MOS transistors have a common carrier concentration level among the source regions, the drain regions and the channel regions, and voltage is produced by using the difference of work function between different gate electrodes formed with respective, different impurity concentration levels and/or with respective, different conductivity types.
Patent Reference 1 relates to a MOS transistor circuit operating stably at high temperatures, wherein it should be noted, with such a circuit using polysilicon gate for the MOS transistors, the variation of resistance value of the gate electrode induces variation of threshold characteristics of the MOS transistors.
Further, with such a circuit, there is provided a resistance body formed of a polysilicon pattern, wherein such a polysilicon pattern used for a resistance body has an impurity concentration level different from the impurity concentration level of the polysilicon patterns used for the gate electrode. Thus, the influence of hydrogen during the fabrication process is different between different polysilicon patterns.
Non-Patent Reference 1 discloses the energy band of the gate electrode formed of a polysilicon pattern, wherein Non-Patent Reference 1 describes the relationship between the impurity concentration level (carrier concentration level) in the gate electrode of a MOS structure and the work function of the substrate.
According to Non-Parent Reference 1, there occurs an increase of work function with increase of carrier concentration level and the work function takes a maximum value when the impurity concentration level has reached the value of 5×1019 cm−3. When the impurity concentration level exceeds the foregoing value, on the other hand, there occurs a decrease in the work function. In the state in which the impurity concentration in the polysilicon pattern is smaller than the foregoing value of 5×1019 cm−3 and thus the polysilicon pattern has an increased resistance value, there is a tendency that hydrogen atoms are easily trapped at the grain boundary, leading to large variation of the resistance value.
Similar variation of resistance value occurs also in the case the polysilicon pattern is used for a resistance element.
In relation to the case of using a polysilicon pattern having such an impurity concentration level that can experience heavy influence of hydrogen, there is proposed a technology for suppressing the effect of hydrogen on the resistance value during the device fabrication process for example as set forth in Patent Reference 2, in which a plasma nitride film and a metal interconnection pattern are disposed over the resistance value with the same ratio of coverage area.
Further, there is disclosed a method of covering a region of the resistance body by a metal interconnection layer pattern such that the effect of hydrogen to the polysilicon resistance body from the plasma nitride film formed thereon is interrupted. Reference should be made to Patent Reference 3.
However, none of these prior art allows sufficient degree of freedom for disposing a metal interconnection layer pattern on the polysilicon resistance body, and there has been a problem in that the area over the resistance body cannot be used for providing interconnection patterns.
Further, there has also been a problem, in the case of using plural polysilicon patterns of mutually different impurity concentration levels for the polysilicon resistance body, in that the degree of the influence of hydrogen changes depending on the impurity concentration level of the polysilicon patterns.